In the semiconductor integrated circuit disclosed in Patent Document 1, two clock drivers 13, 14 are disposed on the rims of the lower and upper sides, respectively, of a chip 10, as illustrated in FIG. 7. A clock input pad 11 and a clock input buffer 12 are disposed in the central area of the left side. The signal line extending from the clock input buffer 12 to the clock driver 13 is equal in length to the signal line extending from the clock input buffer 12 to the clock driver 14, thereby reducing skew between signals input to the two clock drivers 13, 14.
Other related techniques are disclosed in Patent Documents 2 and 3.
Patent Document 1: JP-A-5-268016
Patent Document 2: JP-A-2003-132674
Patent Document 3: JPA-11-345255